The present invention relates to a control system for an electronic postage metering system.
It is conventional to design a unique control system for each module of an electronic postage metering system. The control system is configured to meet the needs of the particular model of postage metering system in a cost efficient manner. The conventional electronic postage meter is comprised of a programmable microprocessor, a plurality of memory units and an application specific integrated circuit (ASIC). The ASIC function is to generate a plurality of system control signals in response to address instruction from the microprocessor. It is therefore conventional to design the ASIC to operate synchronously with the microprocessor. For example, a high speed electronic postage meter control system may include a 32 megahertz microprocessor and compatible application specific integrated circuit. In contrast, a less complex electronic postage meter control system, like that of the Pitney Bowes model 6900 Postage Meter, will include a 8 megahertz microprocessor and compatible ASIC. As a result of this and other variations between EPM models, it is customary to develop a specific ASIC for each EPM model.